There has been a lot of new progress with the OpenBench Logic Sniffer. “Dogsbody” has contributed an exciting new Verilog core that adds some significant improvements:
3.07 OpenBench Logic Sniffer Release
- 3.07 FPGA “Demon” Core
- Fix for 200Mhz sampling in “Demon” Core
- 3.0 PIC Firmware
- SPI speed increase
- Fix for Winbond read issue
- 0.9.3 SP1 Jawi OLS client
- Bug fixes
3.06 FPGA “Demon” Core Release
- RLE works correctly for all memory depths.
- HP 16550a Advanced triggering mode. (The client does not support this yet, but the Verilog core supports triggers just like the HP 16550a!)
- Meta tags inside the FPGA core allow the client to determine the version running on FPGA.
- Jawi’s client “0.9.3.1″ fixes RLE issues, adds JTAG decoder, and 1-Wire decoder.
- Version 2.6 of the PIC firmware increases SPI transfer speed. The difference is noticeable, this release is named “Demon” because it is a speed demon.
- OLS Upgrader works for both Windows and Linux now. A simple menu based GUI steps you through upgrading your OLS.